Static timing analysis - PDFSEARCH.IO - Document Search Engine

Static timing analysis
Results: 58

#	Item
41	Datasheet CustomSim High-performance, high-capacity FastSPICE simulation Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-18 14:15:51 Electronic circuit simulation SPICE Synopsys Power network design Logic simulation Verilog Static timing analysis Reliability engineering Silvaco Electronic engineering Digital electronics Electronic design automation
42	Datasheet NanoTime Transistor-level Static Timing Analysis Solution for Custom Designs Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-27 00:06:11 Signoff Synopsys Static timing analysis Signal integrity Electronic circuit simulation Delay calculation Logic simulation Parasitic extraction SPICE Electronic engineering Electronic design automation Digital electronics
43	PROJECT PROFILE 2A704: Robust design for efficient use of nanometre technologies (ROBIN) EDA FOR SOC DESIGN AND DFM Add to Reading List Source URL: www.catrene.org Language: English - Date: 2009-03-25 10:35:46 Electronic design Integrated circuits Digital electronics Signal integrity Static timing analysis System on a chip Parasitic extraction Electronic circuit MOS Technology SID Electronic engineering Electronics Electronic design automation
44	White Paper The Benefits of Static Timing Analysis Based Memory Characterization September 2012 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:32:46 Integrated circuits Formal methods Signoff Dynamic random-access memory Static timing analysis Electronic design automation Synopsys SPICE System on a chip Electronic engineering Electronic design Electronics
45	White Paper PrimeTime® Mode Merging Reducing Analysis Cost for Multimode Designs August 2013 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:33:39 Static timing analysis Electronic design automation Signoff Timing closure
46	White Paper Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform February 2014 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:32:38 Timing closure Physical design Design closure Integrated circuit design Static timing analysis ECO Synopsys Signal integrity Design rule checking Electronic engineering Electronic design automation Signoff
47	Timing analysis comprehending mask misalignment due to Double Patterning Arvind NV, Ajoy Mandal Texas Instruments India Add to Reading List Source URL: tauworkshop.com Language: English - Date: 2014-04-28 21:47:10 Capacitance Coupling Delay calculation Static timing analysis Physics Mechanical engineering Electricity
48	Technical White Paper High-Performance, High-Precision Memory Characterization Federico Politi, Altos Design Automation, Inc. High-Performance, High-Precision Memory Characterization Add to Reading List Source URL: www.altos-da.com Language: English - Date: 2009-07-14 19:10:38 Computer memory Formal methods Electronic design Altos Design Automation Static timing analysis Integrated circuit design Signoff CPU cache Random-access memory Electronic engineering Electronic design automation Digital electronics
49	Variety MX Improve your view… Variety MX expands on Altos’ Liberate MX macro block characterization capabilities to include statistical timing models that account for both global (systematic) and local (random) proce Add to Reading List Source URL: www.altos-da.com Language: English - Date: 2009-12-15 20:45:08 Formal methods Altos Design Automation Statistical static timing analysis Static timing analysis Timing closure Standard cell SPICE Process variation Synopsys Electronic engineering Electronic design automation Software
50	Liberate LV Improve your view… Liberate LV provides a collection of utilities for validating libraries including functional equivalence checking, data consistency checking, revision analysis and correlation with variou Add to Reading List Source URL: www.altos-da.com Language: English - Date: 2009-07-14 19:09:50 Altos Design Automation Mentor Graphics Synopsys Static timing analysis Verilog Electronic circuit simulation SPICE Electric Cadence Design Systems Electronic engineering Electronic design automation Software